SafeTower

Chief Architect

Various Companies & Startups

I started working with startups as early as 2007 and eventually progressed as a Fractional CTO where I provide ongoing executive-level technology leadership for startups and growth-stage companies across industries including healthcare, AI, fintech, and consumer SaaS. I specialize in aligning technology with business strategy, building remote engineering teams, launching MVPs, and scaling platforms to support hypergrowth. 

Some of my previous and current client’s include:

Opstack AI (opstack.ai) – Architected AI-powered business optimization platform for franchise owners; oversee hiring, engineering strategy and built a high performing offshore team to build MVP

Planned (joinplanned.com) – Launched a consumer app from inception to production in 3 months by building the team and guiding the company's development initiatives pre and post launch

Grouped (grouped.com) – Led the team while we scaled user base from 20K to 300K+ by spearheading the re-architecture of messaging, payments, and live streaming infrastructure; Built new team from the group up to support growth.

Eyerate (eyerate.com) – Led the team through transition for a product that has 28 million+ weekly users across US and Canada, tripled engineering headcount, launched mobile platform and optimized process.

SeeSnap (seesnap.com) – Defined engineering and product strategy for a deskless worker platform; managed global team across 6 countries.

Fivo.io (fivo.io) – Oversaw development of a cloud-native lab data monitoring platform; led team scaling, architecture, and compliance across EDI and health data integrations.

Impart Wealth  (hivewealth.com) – Re-architected backend to event-driven infrastructure; led MVP delivery and development efforts for AI-powered financial advice platform and mobile app.

Overture Health Care (overturehealthcare.com) – Built team and platform from scratch; delivered real-time patient communication tools and led data aggregation strategy for population health analytics.

Fractional Chief Technology Officer / Technical Advisor

Fivo.io

Chief Technology Officer

SeeSnap.AI

Technical Advisor

EyeRate

Vice President Of Engineering

Flourish FI

SkySlope

Engineering Manager

Hive Wealth

Head of Engineering

Overture Health Care

American Health Care Administrative Services

Senior Software Architect / Software Engineering Manager

Engineering Leader | Fractional CTO | Technology Advisor

A highly-effective Engineering Leader with experience in building cloud-scale applications while managing highly-cohesive teams that consistently delivers above and beyond expectations. 

A servant leader who understand that the only way to lead is to serve others.

Specialties: ASP.NET MVC, .NET Core, Javascript, Angular, Ionic Framework, Apache Cordova, Microsoft SQL Server, C#, VB.NET, Java, SQL, Silverlight, WCF, WPF, Business Intelligence, Analytics, Software Architecture, Enterprise Architecture, Design Patterns, Process Development, Microservices, Service Oriented Architecture, Web Services, Domain Driven Design, Event-driven Architecture, Cloud to Cloud Integration, Amazon Web Services, Microsoft Azure, Project Management, Requirements Analysis, CRM, ERP, Netsuite, Application Security, Mentoring, Leadership, Project Management, Agile, Scrum, eCommerce

Keith Oliver Rull

Amazon Lab126

Hardware Engineering Manager (EE)

Sr Hardware Development Engineer

Panasonic Automotive

1. Electrical lead for Head Up Display (HUD) products at PASA serving various OEMs ( GM, Ford, FCA, Toyota, Nissan, JLR etc)
2. Responsible for Electrical Architecture definition for HUDs , schematic capture/simulation, component selection, layout, EBOM creation, testing and validation of product per Automotive OEM specifications

Sr Electrical Engineer

Itron

	Designed ACT-LGA, a 10L-layer HDI ALIC LGA based compact PCB solution to be used as core processing and communication module across various ITRON products such as SMART meters and Gateways as well as standalone product intended for IOT market
	Solution provides high end processing using 400+ pin ARM Cortex processor, NAND/LPDDR along with a DSP core to implement software defined radio schemes and an integrated power management IC. Design provides wireless communication using RF (900 MHz+2.4GHz) and Wi-Fi along with wired communication using USB2.0, Ethernet, SDIO, SPI, I2C and UART.
	Responsible for system definition, schematic capture/simulation, component selection, layout, BOM creation, testing and validation
	Performed Pre and Post layout verification of the circuits for signal integrity and EMI using HyperLynx and Cadence Sigrity.
	Work with CM to aim for DFM/DFA/DFT and identify issues focusing large volume production at maintaining low cost by identifying cost and reliability critical areas such component selection, panel design, component placement and process parameters
	Develop test fixtures and provide electrical test specifications for the large scale manufacturing and testing.
	Create detailed lab test and validations plans including temperature, humidity, surge, drop and EMC/EMI testing.
	Involved in FCC and UL certifications

Design Engineer II

Project: iSOM Application specific integrated circuit      (07/2015 – 06/2016)
	Worked on the ASIC implementation of LGA based iSOM as part of the cost reduction version of the LGA iSOM.
	Involved in architecture and system level specification definition for the multi-chip solution of iSOM that has; a Digital SOC including an ARM cortex core and a DSP; and an RFIC. The solution provides high end processing and communication and at the same time reducing the cost and system footprint.

Project: Land Grid Array (LGA) based implementation of iSOM (Itron System on Module)   (12/2012-06/2015)
	Designed an 8-layer high speed HDI PCB solution used as a standalone product for solid state smart metering solutions for electricity. 
	ARM based design with external FLASH, RAM, PMIC, DSP, PIC and RTC for time keeping with available interfaces as USB 2.0, UART, I2C, SPI, SDIO, Wi-Fi, Ethernet and JTAG with applications intended towards IOT.
	Responsible for system definition, schematic capture/simulation, component selection, layout, BOM creation, testing and validation.
	Performed SI Analysis for high speed interfaces, EMI compliance, characterized system noise, designed test setups and data acquisition scheme using Lab VIEW for testing and verification (ICT, FVT, ALT) aimed at DFM and DFT for volume production
	Work closely with firmware/software engineering team to meet product requirements and resolve any engineering issues.
	Support manufacturing by providing electrical test specifications and process parameters such as solder paste, volume, temperature profile and storage. Help in developing manufacturing test fixtures along with fault detection and rectification support using X-rays and AOI for high volume production

Design Engineer I

Canon Stroke and Vascular Research Center

Solid State X-ray Image Intensifier Array :(2010- present)
•	Developed a novel X-ray imager in modular array, based on the customized fiber optics and Electron-Multiplying CCDs (EMCCD) providing high resolution and extended field-of-view for fluoroscopy and angiography applications.Designed complete electronics to drive the EMCCD sensors, digitize, control and acquire data from multiple imaging modules in real-time. 

Multiple Module Multiplexer Integrated circuit  (2009-2010)
• Designed a custom integrated circuit on 0.5 um ON-SEMI analog/mixed signal process to acquire 12 bit data from multiple indirect X-ray detectors hence enabling large field of view, Region of Interest (ROI) imaging and adjustable spatial resolution for medical X-ray imaging systems.  

CMOS Glare sensor array: (2008-2009)
• Designed, simulated and laid-out a novel CMOS glare sensor array that detects glare at one point in a matrix of picture elements by scanning the matrix for a predetermined threshold level voltage. If the glare is detected than that particular pixel or  array of pixels is automatically adjusted for sensitivity using on chip microcontroller

 FSK Modulator using PLL  (2007 – 2008)
Designed a low power and high bandwidth CMOS integrated circuit to perform FSK modulation.Key components included a VCO, Phase-frequency detector, charge pump, loop filter, frequency divider and a comparator. Ensured minimum layout area using matched layout techniques and avoiding using resistors. Manufactured via 0.6 µm ON-SEMI analog/mixed signal CMOS process technology through MOSIS .Schematic, Layout and Verification was done on Cadence Design suite

CMOS Chip Design for a LED Driver and Photo receiver: (2007-2008)
• Designed, simulated and laid-out for 0.6 micron CMOS LED driver with voltage controlled oscillation (VCO) circuit and photo receiver circuit with high gain amplifier and threshold detection in a single chip using SPICE and Virtuoso.

Research Associate

Poornima College of Engineering

Taught various subjects: Digital Communication, Advance microprocessors, Electronic devices &amp; circuit, Computer Networks,   VLSI technology.
 Labs supervised: Advance microprocessor lab, VHDL/ Verilog Lab, and electronic CAD lab

Lecturer (Electronics and Communication engineering)

	10+ years of experience in Analog/Digital circuit design focusing DFM/DFA for high volume production, reliability, compliance and Low Cost.
	10+ years of experience in pre/post layout characterization for Signal Integrity, Power integrity/PDN design using tools such as ADS, Ansys SIpro/PIpro, Hyperlynx and Cadence Sigrity
	5+ years of experience characterizing and improving EMI/EMC performance for Emissions( RE-ALSE, CE, PEPS) and Immunity ( BCI, ESD, RI-NFPT, CCC, DCC) along with experience in test methodology for EMI/EMC test required for certifications 
	10+ years of experience in layout of multilayer (8/10/12) high speed HDI ALIC PCB design with 400+ pin 0.5 to 0.8 mm pitch BGAs.
	Successfully delivered multiple products encompassing architecture definition, component selection, schematic, floor planning, stackup, layout, BOM creation, test plan and test setup for functionality validation and performance characterization along with compliance. 
	10+ years of experience working with CMs (Domestic and Overseas) for PCB and PCBA focusing large scale manufacturing and testing.
	10+ years of experience in DFM/DFA for complex and highly dense designs
	Developed several data acquisition and processing setups for FVT, ICT and debugging using Lab view and FPGAs

Note:  No Interest in any kind of Coding or SW language.  Pure HW guy

Prateek Sharma

taplio

The Battle

Keith Oliver Rull

Prateek Sharma

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