Boeing Defense, Space & Security

Sr Staff Emulation Engineer

Vadum Inc.

AI/ML Incubator Program Manager

PMDojo | Grow your product mindset

Collaborating with a cross-functional and diverse team to solve the problem of Product-Market fit and problem space identification as a product consultant in 10 weeks at PMDojo. I am helping Humanz Mediate launch a product end to end in the fit market. Check out https://www.pmdojo.me/product-accelerator for more information on what I’m working on.

Product Fellow, Industry Track

Arteris IP

• Led 3-person emulation team for deployment of Ncore 3.0 interconnect with Customer requested ARM CPU to boot mobile SoC for Server and Auto applications on Emulation and Simulation. 
• Created the System Verilog based transactor infrastructure which includes AXI, ACE and CHI testbenches with respective transactors from Mentor working with Arteris Interconnect and ARM CPU connected as one of CHI masters. 
• Worked with vendor to develop cache models of ACE and CHI to enable coherent traffic across the Ncore interconnect using SV testbenches to deliver coherency verification coverage.
• Executed BOOT code working with firmware team and IO experts to bring-up different firmware validation scenarios.

Principal Emulation/Verification Lead

Marvell Semiconductor

Working on Emulation for ThunderX family of ARM processors in Server Processor Business Unit focusing on Cadence Palladium.
•	Led the emulation bring-up of PCIe Gen5 Speedbridge and BOOT code execution and debug on emulation related to IO devices on Palladium emulation. 
•	Successfully brought up PCIe Gen5 Speedbridge connected to ThunderX server SoC emulation model on Palladium to enable IO driver testing and PCIe testing on emulation. 
•	Debugged and supported IO drivers for Ethernet, PCIe Gen5 on the setup to enable early software validation and driver development in pre-silicon time frame. 
•	Supported reduced Linux OS boot debugging boot code, device drivers, high level firmware and services to enable performance and power benchmark testing in emulation.

Principal Engineer

Microsoft

As a contractor on emulation team, provide builds, testbenches and automation for Secure BOOT testing for XBOX SoCs (Palladium-Z1) and GFX-lite models (Zebu-XL) based on vendor provided IP for Graphics and Advanced Processing Units.
=> Responsible for design compilation (ixcom and ice flow), regression setup, hardware setup, test case debug/failure analysis and Integrating new IPs and AVIPs to test various SOC interfaces such as PCIe.
=>	Enabled x86 SoC BOOT from NVMe sequence bringup from 1st build to command prompt in SECURE mode debugging firmware bringup issues on Z1 emulation SoC platform. 
=>	Created GFX-lite builds on Zebu ZS3 and ZS4 platforms to enable testing (triangle test, popix test etc.)
=>	Drove feature enablement such as save-restore and Infinitrace for Palladium by collaborating with CAD team and vendor Application Engineers to enhance emulation performance and debug capabilities. 
=>	Supporting Users encountering issues with emulation workflows, hardware and software.

Qualcomm

Achieved program level alignment for next gen multi-die Centriq chip by working with core leadership team including executive leaders from operations, software, power/performance, validation, product management, PDE, process and program management.
Assisted in timely tapeout for multi million dollar multi-chip Server design for Qualcomm Datacenter division
Co-authored Productization PoR task list and presented to executive committee to align various teams for productization planning and customer milestones and helped create MS Project based task list for Rev1 and Rev2 multi-die Centriq. 
•	program scale in the tens of millions of dollars.
•	Effectively leading cross-functional teams with no direct line supervising relationship.
•	Communicating directly with customers to align timing plans, share schedule risk information and escalate critical issues.
•	Project reviews: Lead weekly reviews of programs with the cross-functional teams and drive actions to meet program goals.
•	Meeting Phase Exit Review criteria and obtaining approval from the Product Council at Phase Exits.
•	Risk mitigation: Leading the team to identify, understand and mitigate risks to any dimension of the triple project constraint: timing, cost, and quality/reliability.

Program Manager

Formulated Palladium Requirement Documents for 8 Use Cases, defining requirements, planning schedule, highlighting risks and dependencies and tracking using Excel to discover software and functional bugs in pre-silicon time frame for one of the largest ever Server SoC chip design leading a team of 3 Sr/Staff engineers and 2 contractors.
•	Cradle to Grave ownership of 8 Palladium Use Cases plans on Palladium by using Excel and JIRA for tracking these Use Cases on Palladium
•	Increased Palladium Use Cases supported from 2 to 8 within 3 years resulting in discovery and resolution of 100+ software and hardware bugs to save silicon steppings at 5-10 million dollars each churn. 
•	Led weekly Vendor meetings and Customer Triage meetings at division level to resolve on average 5+ issues weekly for 90% utilization of One of the 3 largest Palladium systems in the world 
•	Helped my Director with Strategy analysis and ROI financial analysis  reports for Executive Investment Council (EIC) and Top Management to determine strategic options and growth plans managing to grow team resources by 600%
•	100% coverage on Palladium combined with 14 Billion Verification cycles a week (an improvement of upto 3000x vs simulation) on 1st multicore SOC Server at QCOM by providing Technical leadership to team of 3 engineers
Using Emulation models to provide validation platforms for Trahira mobile SoC. Verify SoC IP such as QDSP, Boot processor, peripherals such as eMMC, SPI, UART using firmware BOOT on emulation. Automate emulation flow to streamline the validation flow and provide features to enable content execution in user friendly manner.

SoC Emulation Team Lead

• Devised emulation execution plan on In-Circuit Emulation target on Cadence Palladium emulator using technical meetings, technical workgroups and input from assigned Project Managers
• Effectively plan, schedule, execute, and track key deliverables using Microsoft Project to meet project requirements for server and Fusion Products for AMD.
• Work with various teams such as BIOS, DSM, HDT, Scan, software diagnostics, GPU diags,  to ensure test plan completion and execution
• Helped complete initiatives such as save-restore, Virtual Logic Analyzer debug, Using Serial IO to output debug messages, memory backdoor etc and improve operational efficiency of the emulator
• Proactively managed changes in project, identify potential crises, devise contingency plans
• Generated the coverage map and communicated status updates to upper management in weekly meetings.
• Led first time UEFI System BIOS execution on an AMD emulation platform, debugging several issues and completing targets such as BIOS POST, DiagOS boot, Windows boot. 
• First to execute IOMMU V2 fusion diagnostics for driver validation on emulation and awarded with a division award for successfully debugging several issues.

Sr. Emulation Engineer

Intel

Transactor Based Emulation (EVE Zebu emulator):
@ Achieved release of 1st SystemVerilog based transactor driven Falcon emulation platform for 32-bit Intel x-86 based Atom CPU (Silverthorne) enabling faster pre-silicon verification increasing coverage and reducing TTM.
Hardware In-Circuit Emulation (Mentor Veloce/Vpro emulator):
@ Lead the implementation of the complex ICE platform using Celeron (NWD) CPU board, IO board and memory fpga board as the memory speed bridge to the DDR2 for Intel Atom based SOC called Lincroft. 
@ Executed the north cluster reset, NWD CPU out of Reset, Clock Synchronization, FSB access, Register reads, memory read-write, accessing device registers for Lincroft using an external reset signal provided by the altera fpga on the IO board. 
@ Implemented the Split Speed System by for faster execution using the RAMBO board to act as the speed bridge. OS and firmware development with speeds in the range of 600 khz – 1 Mhz core clock in pre-silicon time frame!!

System Level Emulation Engineer

Leading with over a decade of engineering and program management experience, my tenure at Boeing Defense, Space & Security focuses on enhancing SoC validation through advanced emulation techniques. The role capitalizes on my robust technical expertise, problem-solving skills, ensuring bug-free designs and swift market delivery.

Previously, as an AI/ML Incubator Program Manager, I drove innovation by fostering cutting-edge Vision Learning and Generative AI applications. My cross-functional leadership has been crucial in aligning business objectives with technical execution, facilitating the commercialization of AI/ML-driven products that deliver tangible value to stakeholders.

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