Cisco

ASIC Engineer

Adveos

ASIC Physical Design Lead Engineer

Responsible for Block level Physical Design , RTL to GDSII , including whole steps of PD.

* RTL  Synthesis,
* Floorplan
* Place and Route
* CTS 
* STA
* DRC, LVS verifications
* EMIR

ASIC Physical Design Engineer

Synopsys Inc

ASIC Physical Design Engineer Sr I

Digital and mix signal block level/full chip level implementation (RTL to GDSII) at deep sub micron technologies.
 
* RTL, Synthesis, 
* Floorplan
* Place and Route
* Optimization
* STA 
* DRC, LVS verifications
* GDSII

ASIC Physical Design Engineer II

Experienced Physical Design Engineer, working on Chip Block level implementation from RTl to GDSII.
Have worked with different technology nodes, (UMC22, TSMC 16, TSMC7, etc.).
Like to work on blocks of high complexity level ( ex. includes different analog IPs).

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