Harshini Yerra's Linkedin Analytics

15yrs + experience in the semiconductor industry as Systems test Architect, x86 performance benchmarking and workload analyst, Post Silicon Validation Lead & Manufacturing Test Solutions Developer. Passionate about designing & conducting Proof of Concept experiments, analyzing complex Data to arrive at state-of -the-art solutions. - Networking workloads characterization, power and Performance Analysis on x86 architecture for influencing future product generations. - Systems Test Architect focusing on Hardware & Software co-development, validation and manufacturing test Quality for IO interfaces towards DPM( defects per million) reduction across SOC, ADAS and server product segments. - Post-Silicon Platform debug lead, diagnostics & test methods architect and Program Manager. - Solutions and Capability Enabling PDE for Stress Test and System Level Test driving towards Mfg test cost reduction and process optimizations. - Exposure to Pre-silicon validation and DFT Verification via prior internships at Intel Corporation and Texas Instruments, India. - Recognized as an Inclusive Team player & Lead with Excellent verbal and written communication skills.