Cadence Design Systems

Lead Synthesis and Implementation Application Engineer

Qualcomm

Part of a team developing and delivering CPU subsystems . Responsibilities include physical synthesis, constraints generation, low power checks, power-performance-area trade-offs, power analysis for a high-performance, low-power CPU Subsystems.

Responsible for PPA Enhancement, co-ordinating with Physical Design and RTL teams to ensure the requirements with respect to functionality and performance are met from design inception to tapeout. 

Working on ARM & Nuvia CPU cores’ physical synthesis and Implementation at <5nm technology nodes. 

Experience with handling multiple ECOs using Conformal ECO flow.

CPU Synthesis/ Implementation Engineer

University of Florida

Responsibilities include: Designing an automation tool for the establishment of a connection between Hardware and Software platforms used in Hardware Software Verification using Python, Verilog.

Graduate Research Assistant

Graduate Student Researcher involved in projects pertaining to Hardware Software Co-Validation. Responsibilities included establishing connection between Software (Processor in Virtual Platform) and Hardware (IPs in SOC).

Graduate Student Researcher

Vivartan Technologies

Trained in design of Standard Cells using 180nm technology in cadence virtuoso .

Trainee

An individual intrigued by challenges faced during the implementation of a design. Always up for brainstorming new techniques to solve the challenges faced and pour efforts to bring about revolutionary changes with respect to optimizing the design.

Taplio

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