Narayanan Ganesan's Linkedin Analytics

Summary: -> Product Engineering, Customer Engagement, Account management(DRI) (2022-Present) -> Verification|LP|Static|Debug initiatives, Project, Account and Team management. Customer Engagement & support (2019-2022) -> Low power emulation (2017-2020) -> Low power static methodology and automation (2016-2022) -> Low power verification for sub system/SoCs (2015-Present) -> SV-UVM based IP/subsystem verification for optical networking ASICs (2014-2015) -> SoC-IP verification for networking SoCs(2011-2014) -> UPF, CPF based power aware verification for networking/wireless ASICs (2007-2011) -> SoC functional verification for mobile base band SoCs(2003-2007) Highlights: -> Product Engineering architect for low power verification -> Managed mid sized team supporting verification/automotive solutions -> Expert in end-to-end low power methodology development for static, dynamic verification, debug & emulation -> SoC profile DV ownership - TB integration, Env bring up, Verification, Tracking/Managing complete DV release cycle from kickoff to tape out -> Experience in developing System Verilog (UVM) based stand alone & SoC level verification environments. -> Experience in developing power aware verification environments using CPF/UPF power format standards. -> Knowledge of USB2.0/USB3,0 (Host/Device), PCIe, Flash (NAND/PNOR/QuadSPI), MDIO, AXI/AHB/APB. -> Strong scripting & debugging skills.