Hanwha Phasor

RFIC Layout Manager, responsible for full chip layout and tape-out of Ku-band RF receivers and transmitters.

RFIC Layout Manager

RFIC Layout Team Lead responsible for full chip layout and tape-out of RF receivers and transmitters.

IC Layout Team Lead

HCL Technologies

Analog Layout Manager responsible for layout for analog/mixed-signal modules, executing layout projects for clients, mentor a team of junior engineers, develop automation scripts, layout reviews and quality assurance. 
I am currently leading a team of 2 designing layouts of  PMIC for 400Gbps SERDES in TSMC40nm. My responsibilities include, layout design of Oscillator, LDO. Top level routing, project management & tracking and development of custom automation scripts.

Technical Manager - RF/Analog Layout

MaxLinear

RFIC layout engineer responsible for top level and  block level layouts in the receiver module of 400Gbps SERDES in TSMC16FF. My responsibilities include the layout design for CTLE, Receiver Top, Inductor designs, electromagnetic modelling and EMIR sign-off

RFIC Layout Engineer (Contract)

RFIC layout engineer, responsible for top level and  block level layouts in the Transmitter module of 45GHz RF Transceiver in UMC 20nm. My responsibilities include the layout design for 5-15GHz Power Amplifier, Top Level Placement and routing, Inductor designs, electromagnetic modelling and EMIR sign-off.

Texas Instruments

Layout Engineer, responsible for top-level and module level layouts for high performance analog modules. During my tenure at TI, I have designed layouts for SAR ADC, Pipeline ADC in TI 65nm process and HV Power Amplifier for Ultrasound Application in Vanguard 0.5um SOI Process

Layout Engineer

Qualcomm

Sr. Layout Engineer, responsible for layout design for GPIOs and Power clamps that would go into Qualcomm's SnapDragon Processors

Senior Layout Engineer

Intersil

Mask Designer-3, responsible for layout for Analog/Mixed signal modules. During my tenure at Intersil, I have designed in block level and module level layouts for PMICs  Sigma=Delta ADC in VIS 0.25um process and High Frequency PLL in TSMC40nm.

Mask Designer

Cosmic Circuits

Lead Analog Layout Engineer, responsible for block level and top level layouts for Analog and Mixed signal circuits. In my last assignment, I led the Connectivity layout group and was responsible for IP and Testchip delivery of MIPI M-Phy and D-Phy IPs. A brief  list of modules I have done here is given below.* MIPI M-Phy in TSMC 40nm, TSMC 65nm
* MIPI D-Phy in TSMC 110nm 
* WLAN AFE Sub Blocks in TSMC 40nm, TSMC 65nm, UMC 40nm, UMC 65nm
* SAR ADC  in TSMC 40nm, TSMC 65nm, TSMC 130nm, UMC 40nm, UMC 65nm
* PLL in TSMC 90nm
* LDO in TSMC 40nm, TSMC 65nm, UMC 40nm, UMC 65nm
* Bandgap in TSMC 40nm, TSMC 65nm, UMC 40nm, UMC 65nm, GF65nm

Lead Analog Layout Engineer

Caterpillar India Private Limited

Responsible for trouble shooting faults in CNC machines

Maintenance Engineer

Analog Layout engineer with 15+ years in Analog/RFIC layouts for varied chips/blocks including 400Gbps SERDES, RF Transceiver, ADCs, PLLs, Serial Interfaces in technologies ranging from 14nm to 0.5um

I have a strong experience in handling the entire Layout Development Cycle, right from project estimation till the Tapeout. As a part of my job, I am responsible for PDK Setup, rule-deck qualification, development of layout constraints, Quality Assurance (DFM, ESD, EM-IR Constraints) in addition to recruitment and training. I was also responsible for fixing tool related issues with EDA vendors and was closely involved in the qualification for PVS, a physical verification tool from Cadence.

Taplio

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