Preetam Alluri's Linkedin Analytics

(On to 3nm PD currently after 5nm, 7nm, 14nm,........) Physical Design and implementation on CPU/GPU on Low Power design, High performance Servers and SOCs and ASICs. IP development High Speed Serdes. •Physical design and implementation for multi-million gate large blocks of varying complexities using RTL to GDSII flow right from Synthesis -> Floorplanning -> Partitioning -> Scan Insertion -> Clock Tree synthesis(CTS)-> Place&route (P&R) -> Static timing analysis to Physical verification( Power grid analysis, Electromigration, IR drop, LVS, DRC, DFM) for multiple tapeouts. .Unit integration. •Semi-custom and full custom structured datapath macros with hands on layout and physical verification experience with Hands on experience with industry standard tools. •Register file and Datapath designs. •Design for Test(DFT) experience in BIST ( Memory and Logic BIST) Macro Test structure verification and ATPG.