Cisco

ASIC Physical Design Engineer

Microsoft

Physical Design Engineer

Physical Design Contract on 7nm Designs

Novus Resources

Custom and Semi Custom Implementation team developing and delivering IPs, Flows and methodology for high speed and targeted PPA goals on 7nm/10nm designs.

Physical design implementation (Placement, CTS, STA) in advanced technologies. STA tool and timing closure methodologies Power grid, clock tree, and low-power reduction implementation methods Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing Physical Verification, Conformal Low Power (CLP), IR drop analysis.  

 

Minimum Qualifications:

5+ years of industry experience in the following technical areas: Physical design implementation (Placement, CTS, STA) in advanced technologies. STA tool and timing closure methodologies Power grid, clock tree, and low-power reduction implementation methods Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification Programming and scripting skills (Tcl, perl and/or C) Strong verbal and written communication skills

Physical Design Contract for Qualcomm QCT Division: 5G Modem, Mempry IP

Encore Semi

IBM Power9 Project dd2 (14nm)
Physical Design and unit integration High Speed IO SerDes - 14nm
PCIE GEN4.

•	Delivered critical Physical Design sections on IBM power  SOC design at block level, unit level and chiplevel  Million+ cells Sections in 14nm design IP using synthesis RTL-GDSII and semi-custom physical integration flows for High performance CPU, GPU and SOC designs. 
•	Delivered Physical Design on the IBM power9 DD2 SOC, on the Global Foundries IO IP team, performed physical design and Physical integration on IOP_X844 in the 14nm design process.
•	Performed Static timing analysis, solved timing violations, buffer solutions, fixed slew violations and coupling issues.
. Developed and improved PD flows to improve the effectiveness and the efficiency of the design process.
•	Extensively used IBM, Cadence and Synopsys physical design verification tools, performed DRC, LVS and NMC analysis- fixing metal density violations,  performed routing, fixed opens and shorts, added redundant vias, checked missing vias and solved metal density issues.
•	Delivered for multiple design promotes and releases to meet the Chip integration requirements.

Physical Design Contract Engineer(CPU/GPU/IO/SOC) - Global Foundries P9  IOP Project

Hardware Engineer on Next Generation High Performace Power Processor/SOC

Processor Design Engineer

*PHYSICAL DESIGN AND IMPLEMENTATION (Physical Design and Semi-Custom Circuit DESIGN) 
- IBM Z series Physical Design: 22nm
- Games Processors, Xbox 360 – CPU and GPU (22nm, 32nm, 45nm and 65nm)

*Delivered Semi-Custom circuits for Processor Memory Interface unit of the CPU chip and delivered high quality macros from design to chip tapeout.
* Floorplan, place and route and pin and power abstracts, routing congestion analysis and generated repeater methodology for the unit to assist timing closure.
*Delivered Complex large blocks(Synthesis macros) in multiple units through RTL to GDSII flow involving, floorplanning, placement, clock tree synthesis, timing optimization, route flows and physical verification (including DRC, LVS, Signal integrity, noise, EMIR and Power).

*Delivered Logic changes for test insertion, scan chain optimization and design ECOs, improved performance and accomplished test time reduction.
*Performed Electrical rule checking to verify test logic connection and responsible for formal equivalency  checking on the RTL releases.

PowerPC464 Embedded Graphics processing unit – FPU (65nm)
*Designed Full custom Floating point Register file (32x33 bit) for a floating point unit (FPU) achieved 25% performance improvement over its predecessors.

Apple G5 PPC Processor (90nm)
*  Power gating, Clock gating and timing fixes   for 4 units ISU,ISV, CIU and L2 cache.


*DFT * Test chip(22nm)
- Led the DFT to evaluate key custom arrays for a testchip prior to production tapeout to ensure hardware success.

*Games processors-xbox360
- Led a  team to deliver LBIST(CPU and GPU) AC manufacturing pattern generation and validation.

Staff Engineer

Oracle

- Circuit design engineer, proficient in full custom and synthesis based Circuit design.
- Full Custon Static and dynamic circuit design.
- Contributed to Ultrasparc V processor (140 Million transistors) from design to tapeout. 
- Designed and implemented multiple complex subblocks through design to tapeout in 90nm process technology from Texas Instruments.
- Spice simulations, Critical path simulations..
- Static timing analysis on innovative and aggressive circuits to alleviate any timing bottlenecks (in both Late and early mode), for both internal and global critical timing paths.
- Electrical verification, Layout and Physical verification in the course of Design implementation.
- Design champion for DFT, led a team of 3 members to accomplish backend flow analysis for the cluster.

MTS Hardware Engineer

Atmel Corporation

- Created verilog test benches for standard cell components verification.
- Worked with CAD tool vendors to enhance and develop available CAD tools.

Graduate Intern

(On to 3nm PD  currently after 5nm, 7nm, 14nm,........)
Physical Design and implementation on CPU/GPU on  Low Power design, High performance Servers and  SOCs and ASICs.

 IP development High Speed Serdes.

•Physical design and implementation for multi-million gate large blocks of varying complexities using RTL to GDSII flow right from Synthesis -> Floorplanning -> Partitioning -> Scan Insertion -> Clock Tree synthesis(CTS)-> Place&route (P&R) -> Static timing analysis to Physical verification( Power grid analysis, Electromigration, IR drop, LVS, DRC, DFM) for multiple tapeouts.

.Unit integration.

•Semi-custom and full custom structured datapath macros with hands on layout and physical verification experience with  Hands on experience with industry standard tools.

•Register file and Datapath designs.

•Design for Test(DFT) experience in BIST ( Memory and Logic BIST)  Macro Test structure verification and ATPG.

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