Rakeshkumar S.'s Linkedin Analytics

SUMMARY OF SKILLS • Over 11 years of engineering experience that covers multiple aspects of ASIC/SoC/IP Verification. Expertise at handling multiple projects, multiple protocols, and working with clients in different time zones at a time within a single organization. Mentoring entry-level engineers and helping organizations to grow in terms of improving the quality of verification solutions delivered to the market. • In-depth knowledge of entire chip design process including IP/SoC Verification Flow, Micro-architecture features, PCIe Express (Gen 1 to Gen 5), CXL 1.1 IP and SoC Verification, IA32 architecture CPU Verification and Validation. Developing complete UVM testbench from scratch after understanding the design specifications, Expertise at developing Test Plan and Function Coverage Plan looking at the design specification. Proficient at Functional Coverage and Code Coverage analysis and providing feedback to the verification team. Expertise at root causing regression failures to Test Issues, Environment Issues, and RTL bugs in shorter duration. • Extensive hands-on experience in RTL design verification using System-Verilog and UVM Methodology. • In-depth knowledge of IA32 Architecture, PCIe Express Protocol(PCIe Gen 1 to PCIe Gen 4). Having a basic understanding of PCIe Gen 5 and CXL 1.1 protocols. Complete knowledge related to PCIe protocol enhancements targeted towards server domain(PCIe SR-IOV, PCIe MR-IOV, and PCIe NVMe). Ramping up on solutions like USB over PCIe. • Significantly contributed to Industry-standard protocol development forums. – PCIe Express(PCI SIG Member) • Collaborative team player with strong technical, communication, and problem-solving skill. TECHNICAL PROFICIENCIES: • Programming/Scripting Languages: Verilog, System Verilog, C, C++, TCL, Perl. • VIP(Verification IP Development): PCIe Gen 3 TL Layer VIP module owner, PCIe SR_IOV VIP solution architect and developer, PCIe Physical Layer 8b/10b encoder/decoder VIP architect and developer, PCIe Gen 3 Physical Layer LTSSM(FSM) module development architect and developer(LTSSM Specific Verification), Resolving VIP bugs filed by customers in shorter duration, Helping customers to verify the initial version of RTL with hotfixes. • Protocols: IA32 CPU Architecture, PCIe Gen1 to Gen5, CXL 1.1, PCIe NVMe, PCIe SR_IOV, PCIe MR_IOV • Methodology: UVM, • Tools: Synopsys VCS, ModelSim, Verdi, DVE, Verdi, Design Compiler, FPGA debugger, Protocol Analyzer, Logic Analyzers, debugger, and Oscilloscopes, Mentor Tools, Cadence NCsim, Cadence vManager, Cadence Xillium Simulator.