Physical Design Engineer

Intel Corporation

Part of Clock team in Xeon Server Group in Intel:
> Fine experience with CAD tools: ICC2 Compiler, PT-PX(Prime Power). 
> Worked in the clock routing part for various partitions/blocks making sure that the skew and latency is well balanced. 
> Hands-on experience in PnR/APR runs.
> Performed timing sign-off/timing closure  at various levels for hold and set-up checks.
> Familiar with low power fundamentals like VCLP, UPF, Clock Gating, Power Gating.
> Performed FSDB runs.
> Generated power roll-up reports for different blocks using Prime-power Synopsys tool and did leakage power analysis with Swapping of cells i.e., LVT to  HVT/SVT. 
> Hands-on experience in physical verification sign-off which involves  DRC, ERC, LVS, IR and antenna checks.

Graduate Technical Intern

I'm currently working as Physical Design Engineer in ARM POP(Processor Optimised Package) IP implementation team. 

Prior to this, I worked in Intel Technology India Pvt Ltd for my 10 months internship, wherein I was into CTS team of XEG Department (Xeon Engineering Group) wherein I was involved in tasks related to clock optimisation. I primarily worked in Clocking, APR, physical verification sign-off & Low Power Implementation for next generation Intel Data Centre Products. 

I hold a MTech Degree in VLSI Design from Vellore Institute of Technology and a B.Tech Degree in ECE from IGDTUW, Delhi.

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