Prodigy Technovations Pvt Ltd

> FPGA based product development from requirement analysis till final product testing in lab environment.
> Verilog based design and testbenches.
> Vivado based design flow.
> Architecture and micro-architecture design.
> Debugging the design using ILA & VIOs.

FPGA Design Engineer

Liebherr Aerospace and Transportation

FPGA Design & Development for Flight Control Systems according to RTCA DO-254 standards
  • VHDL coding – RTL, package and testbench, Simulation,  Synthesis , Timing Analysis, I/O pin 
     assignment, Place & Route, Static Timing Analysis, Bitstream generation

  • Model-based approach – Fixed-point analysis, Optimizing the resource utilization on FPGA, 
     Eliminating the Multi-cycle path, generating the VHDL code from the Simulink model using HDL 
     Coder, Synthesis, Timing Analysis, I/O pin assignment, Place & Route, Static Timing Analysis, 
     Bitstream generation

  • Linting or verifying the design to implement it on board and measuring the signals using 
    Oscilloscope

  • Utilizing the IP cores like Core AHB SPI for the interface between FPGA and Microcontroller and 
     handling the R/W operations

• Tools Used: Libero SoC, MATLAB, Simulink, AlintPro, Microsemi IGLOO2 FPGA, FlashPro

Digital Design Engineer (FPGA Development)

"Optimization of the Motor Control and Regulation Model implementation for a Permanent Magnet Synchronous Motor (PMSM) on an FPGA"

Aim- To optimize the speed & area of the Motor Control model on an FPGA.
Tasks: Clock rate pipelining, Resource sharing, Timing Analysis (critical path analysis, eliminating negative slack) and Static Timing Analysis (STA), Eliminating Multi-cycle paths, Optimizing the FPGA clock frequency, Optimizing the PWM resolution, Optimizing the power consumption.

Tools used: MATLAB, Simulink, Libero SoC, Microsemi IGLOO2 family FPGA

Master Thesis Student

WorldServe Education

1) Digital Image Processing algorithms in MATLAB and modeling in Simulink for the target applications
    •  "A novel automatic low cost cutting machine cum 3D printer using image processing based 
        control". Was responsible for developing Image Processing algorithms like: Color Conversion, 
        Segmentation and Morphological Operations 
    • "A novel video processing based smart helmet for rear vehicle intimation and collision avoidance".  
       Was responsible for developing Image Processing algorithms for rear vehicle intimation and 
       extending the algorithms in developing an indicator system during the lane change over
    • Synthesis, Simulation, HDL Code (Verilog) and Netlist generation, Timing Analysis, Optimizing and 
       implementing the cost- effective design on board
    • Authored and presented these two research works in international IEEE-Conferences

2) Programming the Arduino Uno with Embedded C for a prototype of automated car
    • Proximity sensors: Object detection for Parking assistance
    • Photo sensors: Automatic switching of the car headlights
    • Interacting with the team for: component selection, integrating various sensor modules on one 
      chip, circuit designing, soldering and verification

Tools Used: MATLAB, Simulink, Xilinx ISE, Xilinx System Generator, Spartan 3E FPGA, Arduino Uno

Research Associate

"Innovative Smart Helmet for Safety Riding Using Processing on FPGA"

Tasks: Image pre-processing, Segmentation, Morphological Operations, Decision making algorithms for rear vehicle intimation in MATLAB and Simulink and later, system generated HDL code (Verilog) for Spartan 3E FPGA. Synthesis and simulation were done using Xilinx ISE

Bachelor Thesis Student

Experience in: FPGA Design from requirement analysis till final product testing in lab environment.
Skilled in: Verilog/VHDL for design and testbenches, architecture and micro-architecture design, and using ILA, VIOs to debug the design.

Also:
- Conducted a workshop in association with World Serve at KSSEM in 2015 on 'Using MATLAB/Simulink for developing Digital Image Processing algorithms targeting an FPGA'.
- One of the jury panelists for All India Paper Writing Competition on Emerging Research (PaCER 2020).
- Researcher, author and presenter of two research papers in IEEE conferences.
Read the papers: 
1) DOI: 10.1109/IBSS.2015.7456641
2) DOI: 10.1109/CoCoNet.2015.7411281

Achievements:
Won the "Best poster presentation" award in an international IEEE conference, IBSS-2015, Mumbai, India.

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